/*=============================================================================
# FileName    :	set_parameter.v
# Author      :	author
# Email       :	email@email.com
# Description :	通过avalon-mm总线快速设置FPGA需要的参数
# Version     :	1.0
# LastChange  :	2019-04-08 20:14:43
# ChangeLog   :	
=============================================================================*/

`timescale  1 ns/1 ps

module set_parameter #
(
    parameter               WIDTH = 128
)
(
    input   wire                csi_clk,
    input   wire                rsi_reset_n,

    /*port*/
    input   wire [01:00]        avs_address,
    input   wire                avs_write,
    input   wire [31:00]        avs_writedata,
    output  reg  [WIDTH-1:00]   coe_parameter_out
);

wire    [WIDTH-1:00]             user_parameter;

// avalon mm 总线处理逻辑, 接收总线数据
set_parameter_register set_parameter_registerEx01
(
    .csi_clk           (    csi_clk           ),
    .rsi_reset_n       (    rsi_reset_n       ),
    .avs_address       (    avs_address       ),
    .avs_write         (    avs_write         ),
    .avs_writedata     (    avs_writedata     ),

    .user_parameter    (    user_parameter    )
);

set_parameter_logic set_parameter_logicEx01
(
    .csi_clk           (    csi_clk           ),
    .rsi_reset_n       (    rsi_reset_n       ),
    .parameter_in      (    user_parameter    ),
    .parameter_out     (    coe_parameter_out )
);

// 根据总线数据, 实现自定义逻辑

endmodule
